Senior DSP FPGA Engineer


Dublin, CA, USA

Full time

Trucks VC portfolio

Aug 18

Become a leader in building a safer future.

AEye is the premier provider of intelligent, next generation, adaptive LiDAR for advanced driver-assistance, vehicle autonomy, and industrial applications that save lives and propel the future of transportation and mobility. We are technology thought leaders who value innovation to create reliable products that save lives. The company's 4Sight™ Intelligent Sensing Platform focuses on what matters most: enabling faster, more accurate and reliable perception for dynamic applications ranging from autonomous driving to intelligent infrastructure, which require precise measurement imaging to ensure safety and performance. AEye was founded in 2013 and is based in the San Francisco Bay Area. We believe in a creative atmosphere, with open, collaborative idea-sharing, where all employees are empowered to achieve their potential. Come experience our flexible and collaborative work environment!

AEye is looking for a highly motivated DSP FPGA Engineer. The individual will be expected to work with a dynamic, talented team of hardware and software engineers developing state-of-the art Lidar technology and products. A wide breadth of previous experience and technical acumen will allow the candidate to participate collaboratively in all levels of the design process, from concept and architectural definition through detailed fpga algorithm implementation, primarily targeting (but not necessarily limited to) MEMS mirror platform drive & control. 

Essential Skills & Experience Requirements (required):

  • BS or Masters in Electrical and/or Computer Engineering.
  • Minimum of 3-5 years industry experience.
  • Hands on FPGA Design Experience using Verilog/SystemVerilog or VHDL for Xilinx or Altera devices.
  • Track record of completed, successful design implementations.

Preferred Skills & Experience (Highly Desired):

  • Experience designing DSP blocks (IIR, FIR) in Matlab and mapping them to FPGAs.
  • Design with DSP & Math IP Core resources. 
  • Proficient with Matlab (Simulink) or similar/equivalent analytical tools.
  • Proficient in DSP and implementing IIR filters in FPGAs. 
  • Experience using Modelsim and/or QuestaSim to develop self-checking testbenches.
  • Experience in a fast-paced and demanding start-up experience. 
  • Demonstrable real-world "cradle-to-grave" product development and support experience; design for manufacturability, design for test, mature product support.
  • Good communication & collaboration skills; able to produce quality documentation for both internal & external target audiences.

Preferred Skills & Experience (Nice to have):

  • Experience implementing closed loop control (PID loops) using VHDL/Verilog in an FPGA/ASIC.
  • Experience with FPGA SOC architecture and design, AXI-Bus, Memory & Data Flow.
  • Experience with Xilinx Zynq Architecture and Vivado tool chains. 
  • Experience with writing low-level c code for test and debug purposes.

AEye, Inc. is proud to be an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, ancestry, pregnancy, sexual orientation, gender identity, national origin, age, citizenship, marital status, disability or Veteran status.

AEye, Inc. participates in E-Verify.

To all recruitment agencies: AEye will not accept agency resumes for this role. Please do not forward resumes to our jobs alias, AEye employees or any other organization location. AEye is not responsible for any fees related to unsolicited resumes.

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